// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
 * Copyright (C) 2020 frank@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN50IW9_H_
#define _DT_BINDINGS_CLK_SUN50IW9_H_

#define CLK_OSC12M		0
#define CLK_PLL_CPUX		1
#define CLK_PLL_DDR0		2
#define CLK_PLL_DDR1		3
#define CLK_PLL_PERIPH0		4
#define CLK_PLL_PERIPH0_2X	5
#define CLK_PLL_PERIPH1		6
#define CLK_PLL_PERIPH1_2X	7
#define CLK_PLL_GPU		8
#define CLK_PLL_VIDEO0		9
#define CLK_PLL_VIDEO0_4X	10
#define CLK_PLL_VIDEO1		11
#define CLK_PLL_VIDEO1_4X	12
#define CLK_PLL_VIDEO2		13
#define CLK_PLL_VIDEO2_4X	14
#define CLK_PLL_VE		15
#define CLK_PLL_DE		16
#define CLK_PLL_AUDIO		17
#define CLK_PLL_AUDIO_2X	18
#define CLK_PLL_AUDIO_4X	19
#define CLK_PLL_CSI		20
#define CLK_CPUX		21
#define CLK_AXI			22
#define CLK_CPUX_APB		23
#define CLK_PSI_AHB1_AHB2	24
#define CLK_AHB3		25
#define CLK_APB1		26
#define CLK_APB2		27
#define CLK_MBUS		28
#define CLK_DE			29
#define CLK_BUS_DE		30
#define CLK_DI			31
#define CLK_BUS_DI		32
#define CLK_G2D			33
#define CLK_BUS_G2D		34
#define CLK_GPU0		35
#define CLK_GPU1		36
#define CLK_BUS_GPU		37
#define CLK_CE			38
#define CLK_BUS_CE		39
#define CLK_VE			40
#define CLK_BUS_VE		41
#define CLK_BUS_DMA		42
#define CLK_BUS_HSTIMER		43
#define CLK_AVS			44
#define CLK_BUS_DBG		45
#define CLK_BUS_PSI		46
#define CLK_BUS_PWM		47
#define CLK_BUS_IOMMU		48
#define CLK_DRAM		49
#define CLK_MBUS_DMA		50
#define CLK_MBUS_VE		51
#define CLK_MBUS_CE		52
#define CLK_MBUS_TS		53
#define CLK_MBUS_NAND		54
#define CLK_MBUS_CSI		55
#define CLK_MBUS_G2D		56
#define CLK_BUS_DRAM		57
#define CLK_NAND0		58
#define CLK_NAND1		59
#define CLK_BUS_NAND		60
#define CLK_MMC0		61
#define CLK_MMC1		62
#define CLK_MMC2		63
#define CLK_BUS_MMC0		64
#define CLK_BUS_MMC1		65
#define CLK_BUS_MMC2		66
#define CLK_BUS_UART0		67
#define CLK_BUS_UART1		68
#define CLK_BUS_UART2		69
#define CLK_BUS_UART3		70
#define CLK_BUS_UART4		71
#define CLK_BUS_UART5		72
#define CLK_BUS_I2C0		73
#define CLK_BUS_I2C1		74
#define CLK_BUS_I2C2		75
#define CLK_BUS_I2C3		76
#define CLK_BUS_I2C4		77
#define CLK_BUS_SCR		78
#define CLK_SPI0		79
#define CLK_SPI1		80
#define CLK_BUS_SPI0		81
#define CLK_BUS_SPI1		82
#define CLK_EMAC_25M		83
#define CLK_BUS_EMAC0		84
#define CLK_BUS_EMAC1		85
#define CLK_TS			86
#define CLK_BUS_TS		87
#define CLK_BUS_GPADC		88
#define CLK_BUS_THS		89
#define CLK_SPDIF		90
#define CLK_BUS_SPDIF		91
#define CLK_DMIC		92
#define CLK_BUS_DMIC		93
#define CLK_AUDIO		94
#define CLK_AUDIO_4X		95
#define CLK_BUS_AUDIO_CODEC	96
#define CLK_AUDIO_HUB		97
#define CLK_BUS_AUDIO_HUB	98
#define CLK_USB_OHCI0		99
#define CLK_USB_PHY0		100
#define CLK_USB_OHCI1		101
#define CLK_USB_PHY1		102
#define CLK_USB_OHCI2		103
#define CLK_USB_PHY2		104
#define CLK_USB_OHCI3		105
#define CLK_USB_PHY3		106
#define CLK_BUS_OHCI0		107
#define CLK_BUS_OHCI1		108
#define CLK_BUS_OHCI2		109
#define CLK_BUS_OHCI3		110
#define CLK_BUS_EHCI0		111
#define CLK_BUS_EHCI1		112
#define CLK_BUS_EHCI2		113
#define CLK_BUS_EHCI3		114
#define CLK_BUS_OTG		115
#define CLK_BUS_LRADC		116
#define CLK_HDMI		117
#define CLK_HDMI_SLOW		118
#define CLK_PLL_PERIPH0_2X_DIV	119
#define CLK_HDMI_CEC		120
#define CLK_BUS_HDMI		121
#define CLK_BUS_DISPLAY_IF_TOP	122
#define CLK_TCON_LCD0		123
#define CLK_TCON_LCD1		124
#define CLK_BUS_TCON_LCD0	125
#define CLK_BUS_TCON_LCD1	126
#define CLK_TCON_TV0		127
#define CLK_TCON_TV1		128
#define CLK_BUS_TCON_TV0	129
#define CLK_BUS_TCON_TV1	130
#define CLK_TVE			131
#define CLK_BUS_TVE		132
#define CLK_BUS_TVE_TOP		133
#define CLK_CSI_TOP		134
#define CLK_CSI0_MCLK		135
#define CLK_CSI1_MCLK		136
#define CLK_BUS_CSI		137
#define CLK_HDMI_HDCP		138
#define CLK_BUS_HDMI_HDCP	139

#endif /* _DT_BINDINGS_CLK_SUN50IW9_H_ */
